1. Field of the Invention
The present invention relates to a synchronizing interface device, and more particularly to a synchronizing interface device for being coupled between and for communicating between computer facilities of computer system having different operating speeds or velocities.
2. Description of the Prior Art
Typical computer facilities, such as the personal computers, may include two or more processing circuits or devices, and may include one or more data buses and/or address buses coupled between the processing devices for communicating between the processing circuits or devices.
However, the processing circuits or devices of the computer facilities may include different operating speeds or velocities. For example, the central processing units (CPU) of the personal computers may include a low operating speed or velocity; and the other computer facilities, such as the personal computer memory card international association (PCMCIA) cards, the lineprinter (LPT) cards, the component object model (COM) ports, of the computer facilities may include a high operating speed or velocity.
It will be relatively difficult to communicate between the processing circuits or devices of the computer facilities that have different operating speeds or velocities. In addition, a great number of errors may be occurred between the processing circuits or devices of the computer facilities that have different operating speeds or velocities.
The present invention has arisen to mitigate and/or obviate the afore-described disadvantages of the conventional synchronizing interface devices.
The primary objective of the present invention is to provide a synchronizing interface device for being coupled between and for communicating between computer facilities of a computer system having different operating speeds or velocities.
In accordance with one aspect of the invention, there is provided a computer system comprising a high speed processing device, a low speed processing device, and a synchronizing interface device coupled between the high and the low speed processing devices, the synchronizing interface device including a read/write assembly coupled between the high and the low speed processing devices, and a delay counting assembly coupled between the high and the low speed processing devices and the read/write assembly for suitably communicating between the high and the low speed processing devices, and for allowing the processing devices having different operating speeds or velocities to be suitably coupled and communicated with each other without occurring errors therebetween.
The synchronizing interface device includes an AND gate coupled between the read/write assembly and the delay counting assembly.
The synchronizing interface device includes an AND gate having a first input coupled to the high speed processing device, and having a second input, and having an output coupled to the low speed processing device, and the synchronizing interface device includes an OR gate having an output coupled to the second input of the AND gate, a first input coupled to the delay counting assembly, and a second input coupled to the high speed processing device.
The high speed processing device includes a card wait port coupled to the first input of the AND gate, and the low speed processing device includes an information waiting port coupled to the output of the AND gate.
The high speed processing device includes an information selecting port coupled to the second input of the OR gate, and the delay counting assembly includes at least one delay counter having a clock port coupled to the first input of the OR gate.
Further objectives and advantages of the present invention will become apparent from a careful reading of a detailed description provided hereinbelow, with appropriate reference to accompanying drawings.